Spicesyntax
Here you can find a short summary of Stanford University:
In TARGET not all components may be implemented. TARGET focuses on PSpice.
The SPICE editor supports help for spice lines with syntax unclarities:
A ... has been expected (partly recognized). The best agreements could be obtained for the following cases, while the syntax is to read as follows:
Examples:
Rname <plus_node> <minus_node> [model] <value>
.SUBCKT <name> <nodes>* [PARAMS: ...]
Tokens in capital letters (and bold) are identifiers
<> is a mandatory field [] is an optional field * is a repetition | divides selectable variants
Commands that TARGET knows:
| Token | Description | Syntax |
|---|---|---|
| .TRAN | Transient-Analysis | .TRAN <print_step_value> <final_time_value> [<no_print_value> [step_ceiling_value]] [UIC] |
| .AC | AC-Analysis | .AC <DEC|OCT|LIN> <points_value> <start_frequency_value> <end_frequency_value> |
| .DC | DC-Analysis | .DC <source_name> <start_value> <end_value> <increment_value> [<source2_name> <start2_value> <end2_value> <increment2_value>] |
| .PROBE | Probe (Save) | .PROBE [[V(<nodes>)] [V(<nodes1>,<nodes2>)] [I(<devices_names>,<pins_values>)]]* |
| .IC | Initial conditions | .IC <V(<nodes>)=<values>>* |
| .NODESET | Nodeset | .NODESET <V(<nodes>)=<values>>* |
| .OPTIONS | Options | .OPTIONS <[PREMA|BADMOS3|KEEPOPINFO|TRYTOCOMPACT] [METHOD=<TRAP|GEAR|TRAPEZOIDAL>] [ABSTOL=<abstol_value>] [CHGTOL=<chgtol_value>] [DEFAD=<defad_value>] [DEFAS=<defas_value>] [DEFL=<defl_value>] [DEFW=<defw_value>] [GMIN=<gmin_value>] [ITL1=<itl1_value>] [ITL2=<itl2_value>] [ITL3=<itl3_value>] [ITL4=<itl4_value>] [ITL5=<itl5_value>] [PIVREL=<pivrel_value>] [PIVTOL=<pivtol_value>] [RELTOL=<reltol_value>] [TEMP=<temp_value>] [TNOM=<tnom_value>] [TRTOL=<trtol_value>] [VNTOL=<vntol_value>]>* |
| PARAMS: | Subckt-Params | PARAMS: <<params_names>=<values>>* |
| OPTIONAL: | Subckt-Optional | OPTIONAL: <<nodes>=<globalnodes_nodes>>* |
| WATCH=<[V(<nodes>)] | Watch | WATCH=<[V(<nodes>)] [V(<nodes1>,<nodes2>)] [I(<devices_names>,<pins_values>)]>* |
| .MODEL | Modelcard resistor | .MODEL <name> <R|RES>([[TC1=<tc1_value>] [TC2=<tc2_value>]]*) |
| .MODEL | Modelcard voltage controlled switch | .MODEL <name> SW([[VT=<vt_value>] [VH=<vh_value>] [RON=<ron_value>] [ROFF=<roff_value>]]*) |
| .MODEL | Modelcard current controlled switch | .MODEL <name> CSW([[IT=<it_value>] [IH=<ih_value>] [RON=<ron_value>] [ROFF=<roff_value>]]*) |
| .MODEL | Modelcard lossy transmission line | .MODEL <name> LTRA([[R=<r_value>] [L=<l_value>] [G=<g_value>] [C=<c_value>] [LEN=<len_value>] [REL=<rel_value>] [ABS=<abs_value>] [COMPACTREL=<compactrel_value>] [COMPACTABS=<compactabs_value>] [NOSTEPLIMIT|NOCONTROL|LININTERP|MIXEDINTERP|TRUNCNR|TRUNCDONTCUT]]*) |
| .MODEL | Modelcard diode | .MODEL <name> D([[IS=<is_value>] [RS=<rs_value>] [N=<n_value>] [TT=<tt_value>] [CJO=<cjo_value>] [VJ=<vj_value>] [M=<m_value>] [EG=<eg_value>] [XTI=<xti_value>] [KF=<kf_value>] [AF=<af_value>] [FC=<fc_value>] [BV=<bv_value>] [IBV=<ibv_value>] [TNOM=<tnom_value>]]*) |
| .MODEL | Modelcard bipolar transistor | .MODEL <name> <NPN|PNP>([[IS=<is_value>] [BF=<bf_value>] [NF=<nf_value>] [VAF=<vaf_value>] [IKF=<ikf_value>] [ISE=<ise_value>] [NE=<ne_value>] [BR=<br_value>] [NR=<nr_value>] [VAR=<var_value>] [IKR=<ikr_value>] [ISC=<isc_value>] [NC=<nc_value>] [RB=<rb_value>] [IRB=<irb_value>] [RBM=<rbm_value>] [RE=<re_value>] [RC=<rc_value>] [CJE=<cje_value>] [VJE=<vje_value>] [MJE=<mje_value>] [TF=<tf_value>] [XTF=<xtf_value>] [VTF=<vtf_value>] [ITF=<itf_value>] [PTF=<ptf_value>] [CJC=<cjc_value>] [VJC=<vjc_value>] [MJC=<mjc_value>] [XCJC=<xcjc_value>] [TR=<tr_value>] [CJS=<cjs_value>] [VJS=<vjs_value>] [MJS=<mjs_value>] [XTB=<xtb_value>] [EG=<eg_value>] [XTI=<xti_value>] [KF=<kf_value>] [AF=<af_value>] [FC=<fc_value>] [TNOM=<tnom_value>]]*) |
| .MODEL | Modelcard junction FET | .MODEL <name> <NJF|PJF>([[VTO=<vto_value>] [BETA=<beta_value>] [LAMBDA=<lambda_value>] [RD=<rd_value>] [RS=<rs_value>] [CGS=<cgs_value>] [CGD=<cgd_value>] [PB=<pb_value>] [IS=<is_value>] [B=<b_value>] [KF=<kf_value>] [AF=<af_value>] [FC=<fc_value>] [TNOM=<tnom_value>]]*) |
| .MODEL | Modelcard MOSFET | .MODEL <name> <NMOS|PMOS>([[LEVEL=<level_value>] [VTO=<vto_value>] [KP=<kp_value>] [GAMMA=<gamma_value>] [PHI=<phi_value>] [LAMBDA=<lambda_value>] [RD=<rd_value>] [RS=<rs_value>] [CBD=<cbd_value>] [CBS=<cbs_value>] [IS=<is_value>] [PB=<pb_value>] [CGSO=<cgso_value>] [CGDO=<cgdo_value>] [CGBO=<cgbo_value>] [RSH=<rsh_value>] [CJ=<cj_value>] [MJ=<mj_value>] [CJSW=<cjsw_value>] [MJSW=<mjsw_value>] [JS=<js_value>] [TOX=<tox_value>] [NSUB=<nsub_value>] [NSS=<nss_value>] [NFS=<nfs_value>] [TPG=<tpg_value>] [XJ=<xj_value>] [LD=<ld_value>] [UO=<uo_value>] [UCRIT=<ucrit_value>] [UEXP=<uexp_value>] [UTRA=<utra_value>] [VMAX=<vmax_value>] [NEFF=<neff_value>] [KF=<kf_value>] [AF=<af_value>] [FC=<fc_value>] [DELTA=<delta_value>] [THETA=<theta_value>] [ETA=<eta_value>] [KAPPA=<kappa_value>] [TNOM=<tnom_value>] [L=<length_value>] [W=<width_value>]]*) |
| .SUBCKT | Subcircuit | .SUBCKT <name> <nodes>* [OPTIONAL: <<interfaces_nodes>=<defaults_nodes>>*] [PARAMS: <<params_names>=<values>>*] ~circuit|.ENDS |
| Xname | Device subcircuit | Xname <nodes>* <model> [PARAMS: <<xparams_names>=<values>>*] |
| Rname | Device resistor | Rname <plus_node> <minus_node> [model] <value> |
| Cname | Device capacitor | Cname <plus_node> <minus_node> <value> [IC=<ic_value>] |
| Lname | Device inductor | Lname <plus_node> <minus_node> <value> [IC=<ic_value>] |
| Kname | Device coupled inductor | Kname <l1_name> <l2_name> <value> |
| Sname | Device voltage controlled switch | Sname <plus_node> <minus_node> <plus_control_node> <minus_control_node> <model> [OFF|ON] |
| Wname | Device current controlled switch | Wname <plus_node> <minus_node> <source_name> <model> [OFF|ON] |
| Vname | Device const voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] |
| Vname | Device pulse voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] PULSE(<initial_value> <pulsed_value> <delay_value> <rise_value> <fall_value> <pulse_value> <period_value>) |
| Vname | Device sinusoidal voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] SIN(<offset_value> <amplitude_value> <freq_value> [delay_value] [damping_value]) |
| Vname | Device exponential voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] EXP(<initial_value> <pulsed_value> <rise_delay_value> <rise_value> <fall_delay_value> <fall_value>) |
| Vname | Device piece-wise-linear voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] PWL([<time_values> <voltage_values>]*) |
| Vname | Device single-frequency FM voltage source | Vname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] SFFM(<offset_value> <amplitude_value> <carrier_freq_value> <modulation_value> <signal_freq_value>) |
| Iname | Device const current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] |
| Iname | Device pulse current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] PULSE(<initial_value> <pulsed_value> <delay_value> <rise_value> <fall_value> <pulse_value> <period_value>) |
| Iname | Device sinusoidal current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] SIN(<offset_value> <amplitude_value> <freq_value> [delay_value] [damping_value]) |
| Iname | Device exponential current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] EXP(<initial_value> <pulsed_value> <rise_delay_value> <rise_value> <fall_delay_value> <fall_value>) |
| Iname | Device piece-wise-linear current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] PWL([<time_values> <current_values>]*) |
| Iname | Device single-frequency FM current source | Iname <plus_node> <minus_node> [[DC] <value>] [AC <ac_value> [ac_phase_value]] SFFM(<offset_value> <amplitude_value> <carrier_freq_value> <modulation_value> <signal_freq_value> |
| Gname | Device linear voltage controlled current source | Gname <plus_node> <minus_node> <plus_control_node> <minus_control_node> <value> |
| Ename | Device linear voltage controlled voltage source | Ename <plus_node> <minus_node> <plus_control_node> <minus_control_node> <value> |
| Fname | Device linear current controlled current source | Fname <plus_node> <minus_node> <source_name> <value> |
| Hname | Device linear current controlled voltage source | Hname <plus_node> <minus_node> <source_name> <value> |
| Bname | Device non-linear dependent voltage source | Bname <plus_node> <minus_node> V=<expression> |
| Bname | Device non-linear dependent current source | Bname <plus_node> <minus_node> I=<expression> |
| Ename | Device poly voltage controlled voltage source | Ename <plus_node> <minus_node> POLY(<dimension_value>) <<plus_control_nodes> <minus_control_nodes>>*{dimension_value} <coefficient_values>* |
| Gname | Device poly voltage controlled current source | Gname <plus_node> <minus_node> POLY(<dimension_value>) <<plus_control_nodes> <minus_control_nodes>>*{dimension_value} <coefficient_values>* |
| Hname | Device poly current controlled voltage source | Hname <plus_node> <minus_node> POLY(<dimension_value>) <source_names>*{dimension_value} <coefficient_values>* |
| Fname | Device poly current controlled current source | Fname <plus_node> <minus_node> POLY(<dimension_value>) <source_names>*{dimension_value} <coefficient_values>* |
| Tname | Device ideal transmission line (TD) | Tname <a_plus_node> <a_minus_node> <b_plus_node> <b_minus_node> <Z0=<z0_value>> <TD=<td_value>>[IC=<va_value>,<ia_value>,<vb_value>,<ib_value>] |
| Tname | Device ideal transmission line (F) | Tname <a_plus_node> <a_minus_node> <b_plus_node> <b_minus_node> <Z0=<z0_value>> <F=<f_value>> [NL=<nl_value>] [IC=<va_value>,<ia_value>,<vb_value>,<ib_value>] |
| Pname | Device lossy transmission line | Pname <a_plus_node> <a_minus_node> <b_plus_node> <b_minus_node> <model> |
| Dname | Device diode | Dname <anode_node> <cathode_node> <model> [area_value] [OFF] [IC=<vd_value>] [TEMP=<t_value>] |
| Qname | Device bipolar transistor | Qname <collector_node> <base_node> <emitter_node> [substrate_node] <model> [area_value] [OFF][IC=<vbe_value>,<vce_value>] [TEMP=<temp_value>] |
| Jname | Device junction FET | Jname <drain_node> <gate_node> <source_node> <model> [area_value] [OFF] [IC=<vds_value>,<vgs_value>] [TEMP=<temp_value>] |
| Mname | Device MOSFET | Mname <drain_node> <gate_node> <source_node> <substrate_node> <model> [[L=<l_value>] [W=<w_value>] [AD=<ad_value>] [AS=<as_value>] [PD=<pd_value>] [PS=<ps_value>] [NRD=<nrd_value>] [NRS=<nrs_value>] [TEMP=<temp_value>] [OFF] [IC=<vds_value>,<vgs_value>,<vbs_value>]]* |
| .MODEL | Modelcard digital input | .MODEL <name> DINPUT(<[S0NAME="<s0name_digitalvalue>"] [S1NAME="<s1name_digitalvalue>"] [S2NAME="<s2name_digitalvalue>"] [S3NAME="<s3name_digitalvalue>"] [S4NAME="<s4name_digitalvalue>"] [S5NAME="<s5name_digitalvalue>"] [S6NAME="<s6name_digitalvalue>"] [S7NAME="<s7name_digitalvalue>"] [S8NAME="<s8name_digitalvalue>"] [S9NAME="<s9name_digitalvalue>"] [S10NAME="<s10name_digitalvalue>"] [S11NAME="<s11name_digitalvalue>"] [S12NAME="<s12name_digitalvalue>"] [S13NAME="<s13name_digitalvalue>"] [S14NAME="<s14name_digitalvalue>"] [S15NAME="<s15name_digitalvalue>"] [S16NAME="<s16name_digitalvalue>"] [S17NAME="<s17name_digitalvalue>"] [S18NAME="<s18name_digitalvalue>"] [S19NAME="<s19name_digitalvalue>"] [CHI=<chi_value>] [CLO=<clo_value>] [S0TSW=<s0tsw_value>] [S0RLO=<s0rlo_value>] [S0RHI=<s0rhi_value>] [S1TSW=<s1tsw_value>] [S1RLO=<s1rlo_value>] [S1RHI=<s1rhi_value>] [S2TSW=<s2tsw_value>] [S2RLO=<s2rlo_value>] [S2RHI=<s2rhi_value>] [S3TSW=<s3tsw_value>] [S3RLO=<s3rlo_value>] [S3RHI=<s3rhi_value>] [S4TSW=<s4tsw_value>] [S4RLO=<s4rlo_value>] [S4RHI=<s4rhi_value>] [S5TSW=<s5tsw_value>] [S5RLO=<s5rlo_value>] [S5RHI=<s5rhi_value>] [S6TSW=<s6tsw_value>] [S6RLO=<s6rlo_value>] [S6RHI=<s6rhi_value>] [S7TSW=<s7tsw_value>] [S7RLO=<s7rlo_value>] [S7RHI=<s7rhi_value>] [S8TSW=<s8tsw_value>] [S8RLO=<s8rlo_value>] [S8RHI=<s8rhi_value>] [S9TSW=<s9tsw_value>] [S9RLO=<s9rlo_value>] [S9RHI=<s9rhi_value>] [S10TSW=<s10tsw_value>] [S10RLO=<s10rlo_value>] [S10RHI=<s10rhi_value>] [S11TSW=<s11tsw_value>] [S11RLO=<s11rlo_value>] [S11RHI=<s11rhi_value>] [S12TSW=<s12tsw_value>] [S12RLO=<s12rlo_value>] [S12RHI=<s12rhi_value>] [S13TSW=<s13tsw_value>] [S13RLO=<s13rlo_value>] [S13RHI=<s13rhi_value>] [S14TSW=<s14tsw_value>] [S14RLO=<s14rlo_value>] [S14RHI=<s14rhi_value>] [S15TSW=<s15tsw_value>] [S15RLO=<s15rlo_value>] [S15RHI=<s15rhi_value>] [S16TSW=<s16tsw_value>] [S16RLO=<s16rlo_value>] [S16RHI=<s16rhi_value>] [S17TSW=<s17tsw_value>] [S17RLO=<s17rlo_value>] [S17RHI=<s17rhi_value>] [S18TSW=<s18tsw_value>] [S18RLO=<s18rlo_value>] [S18RHI=<s18rhi_value>] [S19TSW=<s19tsw_value>] [S19RLO=<s19rlo_value>] [S19RHI=<s19rhi_value>]>*) |
| .MODEL | Modelcard digital output | .MODEL <name> DOUTPUT(<[S0NAME="<s0name_digitalvalue>"] [S1NAME="<s1name_digitalvalue>"] [S2NAME="<s2name_digitalvalue>"] [S3NAME="<s3name_digitalvalue>"] [S4NAME="<s4name_digitalvalue>"] [S5NAME="<s5name_digitalvalue>"] [S6NAME="<s6name_digitalvalue>"] [S7NAME="<s7name_digitalvalue>"] [S8NAME="<s8name_digitalvalue>"] [S9NAME="<s9name_digitalvalue>"] [S10NAME="<s10name_digitalvalue>"] [S11NAME="<s11name_digitalvalue>"] [S12NAME="<s12name_digitalvalue>"] [S13NAME="<s13name_digitalvalue>"] [S14NAME="<s14name_digitalvalue>"] [S15NAME="<s15name_digitalvalue>"] [S16NAME="<s16name_digitalvalue>"] [S17NAME="<s17name_digitalvalue>"] [S18NAME="<s18name_digitalvalue>"] [S19NAME="<s19name_digitalvalue>"] [CLOAD=<cload_value>] [RLOAD=<rload_value>] [S0VLO=<s0vlo_value>] [S0VHI=<s0vhi_value>] [S1VLO=<s1vlo_value>] [S1VHI=<s1vhi_value>] [S2VLO=<s2vlo_value>] [S2VHI=<s2vhi_value>] [S3VLO=<s3vlo_value>] [S3VHI=<s3vhi_value>] [S4VLO=<s4vlo_value>] [S4VHI=<s4vhi_value>] [S5VLO=<s5vlo_value>] [S5VHI=<s5vhi_value>] [S6VLO=<s6vlo_value>] [S6VHI=<s6vhi_value>] [S7VLO=<s7vlo_value>] [S7VHI=<s7vhi_value>] [S8VLO=<s8vlo_value>] [S8VHI=<s8vhi_value>] [S9VLO=<s9vlo_value>] [S9VHI=<s9vhi_value>] [S10VLO=<s10vlo_value>] [S10VHI=<s10vhi_value>] [S11VLO=<s11vlo_value>] [S11VHI=<s11vhi_value>] [S12VLO=<s12vlo_value>] [S12VHI=<s12vhi_value>] [S13VLO=<s13vlo_value>] [S13VHI=<s13vhi_value>] [S14VLO=<s14vlo_value>] [S14VHI=<s14vhi_value>] [S15VLO=<s15vlo_value>] [S15VHI=<s15vhi_value>] [S16VLO=<s16vlo_value>] [S16VHI=<s16vhi_value>] [S17VLO=<s17vlo_value>] [S17VHI=<s17vhi_value>] [S18VLO=<s18vlo_value>] [S18VHI=<s18vhi_value>] [S19VLO=<s19vlo_value>] [S19VHI=<s19vhi_value>]>*) |
| .MODEL | Modelcard digital I/O | .MODEL <name> UIO(<[DRVH=<drvh_value>] [DRVL=<drvl_value>] [DRVZ=<drvz_value>] [INLD=<inld_value>] [INR=<inr_value>] [OUTLD=<outld_value>] [TPWRT=<tpwrt_value>] [TSTOREMN=<tstoremn_value>][TSWHL1=<tswhl1_value>] [TSWHL2=<tswhl2_value>] [TSWHL3=<tswhl3_value>] [TSWHL4=<tswhl4_value>] [TSWLH1=<tswlh1_value>] [TSWLH2=<tswlh2_value>] [TSWLH3=<tswlh3_value>] [TSWLH4=<tswlh4_value>] [DIGPOWER="<digpower_name>"] [ATOD1="<atod1_name>"] [ATOD2="<atod2_name>"] [ATOD3="<atod3_name>"] [ATOD4="<atod4_name>"] [DTOA1="<dtoa1_name>"] [DTOA2="<dtoa2_name>"] [DTOA3="<dtoa3_name>"] [DTOA4="<dtoa4_name>"]>*) |
| .MODEL | Modelcard(timing) digital delayline | .MODEL <name> UDLY(<[DLYMN=<dlymn_value>] [DLYTY=<dlyty_value>] [DLYMX=<dlymx_value>]>*) |
| .MODEL | Modelcard(timing) standard gates | .MODEL <name> UGATE(<[TPLHMN=<tplhmn_value>] [TPLHTY=<tplhty_value>] [TPLHMX=<tplhmx_value>] [TPHLMN=<tphlmn_value>] [TPHLTY=<tphlty_value>] [TPHLMX=<tphlmx_value>]>*) |
| .MODEL | Modelcard(timing) tristate gates | .MODEL <name> UTGATE(<[TPLHMN=<tplhmn_value>] [TPLHTY=<tplhty_value>] [TPLHMX=<tplhmx_value>] [TPHLMN=<tphlmn_value>] [TPHLTY=<tphlty_value>] [TPHLMX=<tphlmx_value>] [TPLZMN=<tplzmn_value>] [TPLZTY=<tplzty_value>] [TPLZMX=<tplzmx_value>] [TPHZMN=<tphzmn_value>] [TPHZTY=<tphzty_value>] [TPHZMX=<tphzmx_value>] [TPZHMN=<tpzhmn_value>] [TPZHTY=<tpzhty_value>] [TPZHMX=<tpzhmx_value>] [TPZLMN=<tpzlmn_value>] [TPZLTY=<tpzlty_value>] [TPZLMX=<tpzlmx_value>]>*) |
| .MODEL | Modelcard(timing) edge-triggered flip-flop | .MODEL <name> UEFF(<[THDCLKMN=<thdclkmn_value>] [THDCLKTY=<thdclkty_value>] [THDCLKMX=<thdclkmx_value>] [TPCLKQLHMN=<tpclkqlhmn_value>] [TPCLKQLHTY=<tpclkqlhty_value>] [TPCLKQLHMX=<tpclkqlhmx_value>] [TPCLKQHLMN=<tpclkqhlmn_value>] [TPCLKQHLTY=<tpclkqhlty_value>] [TPCLKQHLMX=<tpclkqhlmx_value>] [TPPCQLHMN=<tppcqlhmn_value>] [TPPCQLHTY=<tppcqlhty_value>] [TPPCQLHMX=<tppcqlhmx_value>] [TPPCQHLMN=<tppcqhlmn_value>] [TPPCQHLTY=<tppcqhlty_value>] [TPPCQHLMX=<tppcqhlmx_value>] [TSUDCLKMN=<tsudclkmn_value>] [TSUDCLKTY=<tsudclkty_value>] [TSUDCLKMX=<tsudclkmx_value>] [TSUPCCLKHMN=<tsupcclkhmn_value>] [TSUPCCLKHTY=<tsupcclkhty_value>] [TSUPCCLKHMX=<tsupcclkhmx_value>] [TWPCLMN=<twpclmn_value>] [TWPCLTY=<twpclty_value>] [TWPCLMX=<twpclmx_value>] [TWCLKLMN=<twclklmn_value>] [TWCLKLTY=<twclklty_value>] [TWCLKLMX=<twclklmx_value>] [TWCLKHMN=<twclkhmn_value>] [TWCLKHTY=<twclkhty_value>] [TWCLKHMX=<twclkhmx_value>]>*) |
| .MODEL | Modelcard(timing) gated latch | .MODEL <name> UGFF(<[THDGMN=<thdgmn_value>] [THDGTY=<thdgty_value>] [THDGMX=<thdgmx_value>] [TPDQLHMN=<tpdqlhmn_value>] [TPDQLHTY=<tpdqlhty_value>] [TPDQLHMX=<tpdqlhmx_value>] [TPDQHLMN=<tpdqhlmn_value>] [TPDQHLTY=<tpdqhlty_value>] [TPDQHLMX=<tpdqhlmx_value>] [TPGQLHMN=<tpgqlhmn_value>] [TPGQLHTY=<tpgqlhty_value>] [TPGQLHMX=<tpgqlhmx_value>] [TPGQHLMN=<tpgqhlmn_value>] [TPGQHLTY=<tpgqhlty_value>] [TPGQHLMX=<tpgqhlmx_value>] [TPPCQLHMN=<tppcqlhmn_value>] [TPPCQLHTY=<tppcqlhty_value>] [TPPCQLHMX=<tppcqlhmx_value>] [TPPCQHLMN=<tppcqhlmn_value>] [TPPCQHLTY=<tppcqhlty_value>] [TPPCQHLMX=<tppcqhlmx_value>] [TSUDGMN=<tsudgmn_value>] [TSUDGTY=<tsudgty_value>] [TSUDGMX=<tsudgmx_value>] [TSUPCGHMN=<tsupcghmn_value>] [TSUPCGHTY=<tsupcghty_value>] [TSUPCGHMX=<tsupcghmx_value>] [TWPCLMN=<twpclmn_value>] [TWPCLTY=<twpclty_value>] [TWPCLMX=<twpclmx_value>] [TWGHMN=<twghmn_value>] [TWGHTY=<twghty_value>] [TWGHMX=<twghmx_value>]>*) |
| Oname | Device digital output | Oname <interface_node> <reference_node> <model> DGTLNET=<digital_node> <io_model> |
| Nname | Device digital input | Nname <interface_node> <low_level_node> <high_level_node> <model> DGTLNET=<digital_node> <io_model> [IS=<is_digitalvalue>] |
| Uname | Device digital stimulus | Uname STIM(<width_value>, <format_array_value>) <digital_power_node> <digital_ground_node> <nodes>*{width_value} <io_model> [IO_LEVEL=<interface_subckt_select_value>] [TIMESTEP=<stepsize_value>] <commands> |
| .STIM | Digital stimulus commands | .STIM <[<time_values> <state_names>] [LABEL=<label_names>] [<time_values> GOTO <goto_names> <n_values> TIMES]>* |
| Uname | Device digital buffer | Uname BUF <digital_power_node> <digital_ground_node> <input_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital inverter | Uname INV <digital_power_node> <digital_ground_node> <input_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital AND | Uname AND(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NAND | Uname NAND(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital OR | Uname OR(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NOR | Uname NOR(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital XOR | Uname XOR <digital_power_node> <digital_ground_node> <in1_node> <in2_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NXOR | Uname NXOR <digital_power_node> <digital_ground_node> <in1_node> <in2_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital buffer-array | Uname BUFA(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital inverter-array | Uname INVA(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital AND-array | Uname ANDA(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NAND-array | Uname NANDA(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital OR-array | Uname ORA(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NOR-array | Uname NORA(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital XOR-array | Uname XORA(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<in1_nodes> <in2_nodes>>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital NXOR-array | Uname NXORA(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<in1_nodes> <in2_nodes>>*{no_of_gates_value} <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital AND-OR compound gate | Uname AO(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_node><model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital compound OR-AND gate | Uname OA(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_node><model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital AND-NOR compound gate | Uname AOI(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_node><model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital compound OR-NAND gate | Uname OAI(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <output_node><model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate buffer | Uname BUF3 <digital_power_node> <digital_ground_node> <input_node> <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate inverter | Uname INV3 <digital_power_node> <digital_ground_node> <input_node> <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate AND | Uname AND3(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NAND | Uname NAND3(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate OR | Uname OR3(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NOR | Uname NOR3(<no_of_inputs_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_inputs_value} <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate XOR | Uname XOR3 <digital_power_node> <digital_ground_node> <in1_node> <in2_node> <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NXOR | Uname NXOR3 <digital_power_node> <digital_ground_node> <in1_node> <in2_node> <enable_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate buffer array | Uname BUF3A(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_gates_value} <enable_node><output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate inverter array | Uname INV3A(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <input_nodes>*{no_of_gates_value} <enable_node><output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate AND-array | Uname AND3A(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <enable_node> <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NAND-array | Uname NAND3A(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <enable_node> <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate OR-array | Uname OR3A(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <enable_node> <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NOR-array | Uname NOR3A(<no_of_inputs_value>,<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<input_nodes>*{no_of_inputs_value}>*{no_of_gates_value} <enable_node> <output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate XOR-array | Uname XOR3A(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<in1_nodes> <in2_nodes>>*{no_of_gates_value} <enable_node><output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital tristate NXOR-array | Uname NXOR3A(<no_of_gates_value>) <digital_power_node> <digital_ground_node> <<in1_nodes> <in2_nodes>>*{no_of_gates_value} <enable_node><output_nodes>*{no_of_gates_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital pullup/pulldown | Uname <PULLUP|PULLDN> (<number_of_resistors_value>) <digital_power_node> <digital_ground_node> <output_nodes>*{number_of_resistors_value} <io_model> [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital delayline | Uname DLYLINE <digital_power_node> <digital_ground_node> <input_node> <output_node> <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital D-Flip-Flop | Uname DFF (<no_of_ff_value>) <digital_power_node> <digital_ground_node> <presetbar_node> <clearbar_node> <clock_node> <data_nodes>*{no_of_ff_value} <q_nodes>*{no_of_ff_value} <qbar_nodes>*{no_of_ff_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital JK-Flip-Flop | Uname JKFF (<no_of_ff_value>) <digital_power_node> <digital_ground_node> <presetbar_node> <clearbar_node> <clock_node> <j_nodes>*{no_of_ff_value} <k_nodes>*{no_of_ff_value} <q_nodes>*{no_of_ff_value} <qbar_nodes>*{no_of_ff_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital SR-Flip-Flop | Uname SRFF (<no_of_ff_value>) <digital_power_node> <digital_ground_node> <presetbar_node> <clearbar_node> <gate_node> <set_nodes>*{no_of_ff_value} <reset_nodes>*{no_of_ff_value} <q_nodes>*{no_of_ff_value} <qbar_nodes>*{no_of_ff_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |
| Uname | Device digital D-Latch | Uname DLTCH (<no_of_ff_value>) <digital_power_node> <digital_ground_node> <presetbar_node> <clearbar_node> <gate_node> <data_nodes>*{no_of_ff_value} <q_nodes>*{no_of_ff_value} <qbar_nodes>*{no_of_ff_value} <model> <io_model> [MNTYMXDLY=<delay_select_value>] [IO_LEVEL=<interface_subckt_select_value>] |